Digital VLSI Design and Simulation with Verilog. Suman Lata Tripathi

Preface

      Integrated circuits are now growing in importance in every electronic system that needs an efficient VLSI architecture design with low-power consumption, a compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize hardware-software integration for lowering the total cost of product acquisition. So, there is a demand for better technological solutions for advanced VLSI architectures that can be done through hardware description language (HDL). Verilog HDL is one of the programming languages that can provide better solutions in this new era of the VLSI industry. The prefabrication design and analysis of such advanced VLSI architecture can easily be implemented with Verilog HDL using available software tools such as Xilinx and Cadence.

      This book mainly deals with the fundamental concepts of digital design along with their design verification with Verilog HDL. It will be a common source of knowledge for beginners as well as research-seeking students working in the area of VLSI design, covering fundamentals of digital design from switch level to FPGA-based implementation using hardware description language (HDL).

The book is summarized in 10 chapters. Chapters 1 and 2 describe the fundamental concepts behind digital circuit design including combinational and sequential circuit design. Chapters 3 to 8 focus on sequential and combinational circuit design using Verilog HDL at different levels of abstraction in Verilog coding. Chapter 9 includes implementation of any logic function using a programmable logic device such as PLD, CPLD, FPGA, etc. Chapter 10 covers a few real-time examples of digital circuit design using Verilog. Chapter 11 focuses on System Verilog, distinct features, computing Verilog and System Verilog with design example.