Microprocessor 4. Philippe Darche

      Figure 1.21. Indirect indexed zero-page addressing of MCS6502

      A representative, penultimate example is MC6809, which offers 18 variations in mode, combining indexed and indirect addressings with the possibility of automatic post-increment or pre-decrement. This post-increment or pre-decrement is useful for managing a stack's pointer. Table 1.2 summarizes the possible combinations. R represents one of the four registers that can be used for indexing, the classics X and Y and the stack pointers user U and material S. Note the addressings using the program counter at the end. The offset is expressed in complement to 2ⁿ representation.

      Indexed and based addressings with or without offset (based indexed plus displacement addressing mode) can be combined, thus offering, for example, 17 possible variations in the case of microprocessor x86. One example of this use is addressing an array of records, of a vector or of a structure, the base pointing the start of the array and index, an element of the array and the displacement, a field of the element.

      Table 1.2. Combined MC6809 addressing modes

      1.2.4. Other addressing modes

Other modes have been introduced to provide a high-level functionality or to adapt to a specific domain such as digital signal processing (cf. § V3-5.2), to a specific mechanism of a processor or to a component such as an I/O controller (cf. Chapter 3 of Darche (2003)) or a microcontroller (cf. § V3-5.3). Moreover, other modes belong to high-level languages. To finish, some obsolete modes are presented.

      1.2.4.1. Memory-to-memory addressing

      The memory-to-memory transfer functionality is possible in a von Neumann- inspired MPU, but it should be seen as exceptional. This is the continuity of the tendency of CISC processors to implement high-level functionalities in the material. Intel calls this mode “string addressing” for its 8086. It involves addressing the characters of a string, that is, of an array of characters by indirection using both its pointer registers SI (Source Index) and DI (Destination Index). It makes it possible, among other things, to read or write a character and, whether the repeat prefix is conditional or not, to make a copy of it in the main memory. The search function in a string is also available.

      1.2.4.2. (Implicit) stack addressing

      Operands are found implicitly (i.e. they are not named) on the stack which is, we recall (cf. § 4.1), access to LIFO (Last-In/First-Out, push-in/pop-out or push- down/pop-up memory) and implemented in primary memory in modern MPU. The two primitives (i.e. functions) to access it are stacking() and unstacking(), translated into instructions respectively by push() and pop(), for example, in x86 architecture. These instructions implement, internally, an indirect addressing mechanism with the Stack Pointer register (SP), which memorizes the address at the top of the stack. The stack is implemented in main memory, but it can be implemented in the processor. The stacked element is specified with the operand. There are also specific instructions to a register, such as pha/pla (push/pull accumulator onto/from stack) from MC6800, which makes it possible to stack/destack this MPU's accumulator. MCS6502 uses php/plp (push/pull processor status on/from stack) this time for the MPU's context. By extension, stack computers do not explicitly name the operands (zero-operand, one-operand or two-operand addressing). For reading on this subject, see Koopman (1989).

      The NS3200 (Hunter 1987) from National Semiconductor (NS) has broadened access to the stack by offering a mode called top-of-stack, literally “stack top”, which makes it possible to access the data of the so-called summit, since modification of the pointer is not systematic (i.e. dependent on the operation). To finish with this topic, MPUs such as the families Arm^®, PowerPC or MC68000 make it possible to use General-Purpose Registers (GPR) as stack pointers. The addressing mode is of indirect type with auto-increment/decrement.

      1.2.4.3. Bit addressing

The first GPPs (for General-Purpose Processor, cf. § V3-1.1) did not have specialized instructions to manipulate (set at one/zero or extraction) or to test individually the bits of an operand by conditional branching (cf. § 2.4.1). It is generally microcontrollers that possess them as they have to read or modify binary information in memory or at the input–output ports (cf. § 3.1 from Darche (2003)). Thus, the microcontroller 68HC12 from the MC6800 family from Motorola has the instructions bclr (bit clear) and bset (bit set) that initialize respectively at 0 or at 1 one position bit specified with the help of a binary mask (see exercise E2.4) in an address word A. These instructions use this mode associated with pre-studied conventional addressing modes. It should be noted that the addressing space is limited compared to other modes. The example in Figure 1.22 shows a reset at 0 for the MSb (Most Significant bit) of an I/O port in byte format