Electrical and Electronic Devices, Circuits, and Materials. Группа авторов
hetero structure DG - TFET.
Figure 2.14 Transconductance efficiency, gm/IDS with applied gate voltage (VGS) and comparison between double gate hetero and homo structure DG -TFET.
Figure 2.15 Sensitivity of delay time with applied gate voltage (VGS) and comparison between double gate hetero and homo structure DG -TFET.
From Figure 2.15, it has been evident that ιd- hetero< ιd- homo and shows, dealy time with applied gate voltage (VGS) is less sensitive than homo DG-TFT. This is a strong recommendation for low power applications.
(2.7)
Figure 2.16 shows the sensitivity of power delay product (PDP) with applied VGS and a comparison between double gate hetero and homo structure DG -TFET. In term of digital circuit design, power delay product is an important design parameter, correlated with the energy efficiency. From Figure 2.16, it has been observed that PDP is strongly affected with the variation of gate drive voltage (VGS). Lowering the supply voltage (VDS = 0.5V), lowers the PDP in hetero structure DG -TFET.
Figure 2.16 Sensitivity of power delay product (PDP) with applied gate voltage (VGS) and comparison between double gate hetero and homo structure DG -TFET.
2.6 Conclusion
In conclusion, the present chapter summarizes the obtained results by popular device analysis technique, modeling and simulation of DG -TFET. For obtaining excellent performance of DG -TFET, the gate dielectric and band engineering technique has been implemented successfully and its effect on the DC, CV and switching performance have been investigated thoroughly. The DG - TFET shows the excellent device and circuit design characteristics in term of switching current (ION) ~ 4.00 × 10-6 A/µm, leakage current (IOFF) ~ 1.00 × 10-20A/ µm, steep subthreshold swing (SS) ~34.25 mV/decade, ION/IOFF ~ 1014 for HfO2 (k ≈ 25) gate dielectric materials. The bandgap engineering approach in the conventional DG - TFET with high - k gate dielectrics is useful for reduction of ambipolar current (Iamb). During investigation, the suppression of the ambipolar current Iamb ~108 A/µm times has been observed. The TFET-based design with hetero DG - TFET shows better transconductance efficiency (gm/IDS) than homo DG - TFET. The maximum cut-off frequency (fT) ~ 0.65 GHz and GBW ~ 0.66 GHz have obtained the goal of the RF applications. The hetero DG -TFET shows a smaller power delay product (PDP) ~1.1×10-15 watt and delay time (td) order of pico range (~ 600 Picoseconds). The obtained results during investigation for the proposed design supposed to the usability in the field of digital and analog applications in terms of circuit and system design with ultra-low-power applications.
Acknowledgement
Special thanks to Prof. S. C. Mishra, Indian Institute of Technology Kanpur, India, for providing us with valuable suggestions and comments.
References
1. T. Masuhara, IEEE Asian Solid-State Circuits Conference, Jeju, pp. 5-8, 2011.
2. R. -. Yan, A. Ourmazd and K. F. Lee, IEEE Transactions on Electron Devices, Vol. 39, pp. 1704 - 1710, 1992.
3. A. M. Ionescu, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 1.2.1-1.2.8, 2017.
4. U. E. Avci, D. H. Morris and I. A. Young, IEEE Journal of the Electron Devices Society, Vol. 3, pp. 88-95, 2015.
5. J. W. Lee and W. Y. Choi, IEEE Access, Vol. 8, pp. 67617-67624, 2020.
6. W. Y. Choi, B. Park, J. D. Lee and T. K. Liu, IEEE Electron Device Letters, Vol. 28, pp. 743-745, 2007.
7. K. Narimani et al., Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Athens, pp. 75-78, 2017.
8. W. Cao, D. Sarkar, Y. Khatami, J. Kang, J. and K. Banerjee, AIP Advances, Vol 4, pp. 067141, 2014.
9. S. Yang, H. Lv, B. Lu, S. Yan and Y. Zhang, IEEE Access, Vol. 8, pp. 23559-23567, 2020.
10. W. Li and J. C. S. Woo, IEEE Transactions on Electron Devices, Vol. 67, pp. 1480-1484, 2020.
11. N. Guenifi, S.B. Rahi, and T. Ghodbane, Materials Focus, Vol. 7, pp. 866-872, 2018.
12. S.B. Rahi, B. Ghosh, RSC Advances, Vol. 5, pp. 54544-54550, 2015.
13. A. C. Seabaugh and Q. Zhang, Proceedings of the IEEE, Vol. 98, pp. 2095-2110, 2010.
14. K. M. Choi and W. Y. Choi, IEEE Electron Device Letters, Vol. 34, pp. 942-944, 2013.
15. S.B. Rahi, P. Asthana & S. Gupta, Journal of Computational Electronics, Vol. 16, pp. 30-38, 2017.
16. S.B. Rahi, B. Ghosh and B. Bishnoi, Journal of Semiconductors, Vol.36, pp: 034002_1-034002_5, 2015.
17. D. Sarkar, X. Xie, W. Liu, et al., Nature, Vol. 526, pp. 91–95, 2015.
18. A.M. Ionescu, and H. Riel, Nature, Vol. 479, pp.329-337, 2011.
19. E.H. Toh, G.H.Wang, G. Samudra, and Y.C.Yeo, Applied Physics Letters, Vol. 90, pp. 263507e1-263507-3,2007.
20. A. C. Seabaugh and Q. Zhang, Proceedings of the IEEE, Vol. 98, pp. 2095-2110, 2010.
21. I. A. Pindoo, S. K. Sinha and S. L. Tripathi, International Conference on Cutting-edge Technologies in Engineering (ICon-CuTE), Uttar Pradesh, India, pp. 28-32, 2019.
22. H. Liu, S. Datta and V. Narayanan, International Symposium on Low Power Electronics and Design (ISLPED), Beijing, pp. 145-150, 2013.
23. W. Cheng et al., IEEE Journal of the Electron Devices Society, Vol. 8, pp. 336-340, 2020.
24. A. S. Verhulst, D. Leonelli, R. Rooyackers and G. Groeseneken, Journal of Applied Physics, Vol. 110, pp. 024510, 2011.
25. B. Sedighi, X. S. Hu, H. Liu, J. J. Nahas and M. Niemier, IEEE Transactions on Circuits and Systems, Vol. 62, pp. 39-48, 2015.
26. K. Boucart and A. M. Ionescu, IEEE Transactions on Electron Devices, Vol. 54, pp. 1725-1733, July 2007.
27. S. Datta, H. Liu, and V. Narayanan, Microelectronics Reliability, Vol. 54, pp. 861-874, 2014.