Digital System Design using FSMs. Peter D. Minns
you have attempted this question.
The answer is shown in Figure 1.8.
Figure 1.8 Outside world input between states.
Since in this case the outside world input ‘st’ must be equal to zero (denoted by the inverting bar to the left of the input st (as in /st).
That is / means not so /st means not st, i.e. when st = 0, then /st = 1.
Note that outside world inputs always lie along the transitional lines. Also, the reader could be using ‘·’ as well as ‘*’ for ‘AND’. Also, ‘+’ for ‘OR’ in Boolean equations; however, in most cases ‘.’ will be used rather than ‘*’. In some cases no symbol will be used for ‘AND’, as in ‘AB’ to mean ‘A·B’.
The state diagram must also show how the ‘outside world outputs’ are affected. This is achieved by placing the outside world outputs either:
inside the state circle (or square); or
alongside the state circle (or square).
Figure 1.9 shows the outside world outputs P and Q inside the state circles. In this particular case, P is logic 1 in state s0, and changes to logic 0 when the FSM moves to state s1. Output Q does not change in the above transaction, remaining at logic 0 in both states.
Draw a block diagram showing inputs and outputs for the state diagram.
Then turn to Frame 1.10.
Figure 1.9 Placement of outside world outputs.
The block diagram will look like that shown in Figure 1.10.
Figure 1.10 The block diagram for the state diagram shown in Figure 1.9.
Sometimes we show a negating circle to imply that the input is actually inverted (see later).
It is easily obtained from the state diagram since inputs lie along transitional lines and outputs lie inside (or alongside) the state circle. The input st would normally have a negating circle to show it is an active low input. This is common practice.
You may remember that in Frame 1.2 we said that each state had to have a unique state number and that a number of flip‐flops were needed to perform this task. These flip‐flops are part of the internal design of the FSM and are used to produce an internal count sequence; they are essentially acting like a synchronous counter, but one that is controlled by the outside world inputs. The internal count sequence produced by the flip‐flops is used to control the outside world decoder so that outputs can be turned on and off as the FSM moves between states.
In Frames 1.4 and 1.5 we saw the architecture for the Mealy and Moore FSM. In both cases, the memory elements shown are the flip‐flops discussed in the previous paragraph. We look at how the internal flip‐flops are coded in a later chapter.
At this stage it is perhaps worth looking at a simple FSM design in detail. We can then bring together all the ideas discussed so far, as well as introducing a few new ones. Try answering the following questions before moving on:
1 A Mealy FSM differs from a Moore FSM in? (See Frames 1.4and 1.5.)
2 The circles in a state diagram are used to? (See Frames 1.8and 1.9.)
3 Outside world inputs are shown in a state diagram where? (See Frames 1.8and 1.9.)
4 Outside world outputs are shown where? (See Frame 1.9.)
5 The internal flip‐flops in an FSM are used to do what? (See Frame 1.10.)
Please turn to Frame 1.11.
Figure 1.11 shows an example of a single‐pule circuit FSM.
The idea here is to develop a circuit based on the FSM that will produce a single output pulse at its output P whenever its input s is taken to logic 1. The FSM is to be clock driven so it also has an input clock. An additional output L is used to indicate that a P pulse has been produced so the user can see effect of ‘fast’ pulses.
The block diagram of this circuit is shown in Figure 1.11.
Figure 1.11 Block diagram of single pulse with memory FSM.
Figure 1.12 shows a suitable state diagram.