Origin of Power Converters. Tsai-Fu Wu
href="#ulink_044cee50-60c7-5ebd-9373-b5d1edf3bae3">11.4 Analogy of Power Converters to DNA 11.5 Conclusions Further Reading
6 Part II: Modeling and Application 12 Modeling of PWM DC/DC Converters 12.1 Generic Modeling of the Original Converter 12.2 Series‐Shunt and Shunt‐Series Pairs 12.3 Two‐Port Network 12.4 Small‐Signal Modeling of the Converters Based on Layer Scheme 12.5 Quasi‐Resonant Converters Further Reading 13 Modeling of PWM DC/DC Converters Using the Graft Scheme 13.1 Cascade Family 13.2 Small‐Signal Models of Buck‐Boost and Ćuk Converters Operated in CCM 13.3 Small‐Signal Models of Zeta and Sepic Operated in CCM Further Reading 14 Modeling of Isolated Single‐Stage Converters with High Power Factor and Fast Regulation 14.1 Generation of Single‐Stage Converters with High Power Factor and Fast Regulation 14.2 Small‐Signal Models of General Converter Forms Operated in CCM/DCM 14.3 An Illustration Example Further Reading 15 Analysis and Design of an Isolated Single‐Stage Converter Achieving Power Factor Correction and Fast Regulation 15.1 Derivation of the Single‐Stage Converter 15.2 Analysis of the Isolated Single‐Stage Converter Operated in DCM + DCM 15.3 Design of a Peak Current Mode Controller for the ISSC 15.4 Practical Consideration and Design Procedure 15.5 Hardware Measurements 15.6 Design of an H∞ Robust Controller for the ISSC Further Reading
7 Index
List of Tables
1 Chapter 3Table 3.1 Degeneration of TGS and ITGS based on the relationship of voltagesVTable 3.2 Degeneration of ΠGS and IΠGS based on the relationship of currentsITable 3.3 Duality between T‐type and Π‐type grafted switches.
2 Chapter 5Table 5.1 Degeneration of TGS and ITGS based on the relationship betweenV1 an...Table 5.2 Degeneration of ΠGS and IΠGS based on the relationship betweenI1 an...Table 5.3 Duality between TGS and ΠGS.
3 Chapter 9Table 9.1 Duality of the soft‐switching PWM buck and boost converter families...
4 Chapter 12Table 12.1 SSTCs of the general converter for the buck family.Table 12.2 SSTCs of the general converter for the boost family.Table 12.3 SSTCs of the buck‐boost converter.Table 12.4 SSTCs of the Zeta converter.Table 12.5 SSTCs of the boost–buck (Ćuk) converter.Table 12.6 SSTCs of the sepic converter.
5 Chapter 14Table 14.1y‐Parameters of the PWM converters operated in CCM.Table 14.2y‐Parameters of the PWM converters operated in DCM.Table 14.3y‐Parameters of the flyback converter operated in DCM.
6 Chapter 15Table 15.1 Specifications and component values of the proposed ISSC.Table 15.2 Summary of gain parameters for the ISSC operated in the DCM.Table 15.3 Parameters of the P, PI, PID controller tuned with Ziegler–Nichols...Table 15.4 List of the power factor and current harmonics of the ISSC.
List of Illustrations
1 Chapter 1Figure 1.1 Configuration of a power processing system.Figure 1.2 Block diagram of a linear regulator.Figure 1.3 Block diagram of a switching regulator.Figure 1.4 Possible components in a power converter.Figure 1.5 (a) Capacitor–capacitor–switch, (b) inductor–inductor–switch, and...Figure 1.6 Non‐PWM converters: (a) two lift, (b) KY, and (c) re‐lift circuit...Figure 1.7 Power converters with a second‐order LC network and a pair of act...Figure 1.8 Power converters with a fourth‐order LC network and a pair of act...Figure 1.9 Converters with a fourth‐order network: (a) buck derived, (b) boo...Figure 1.10 Converters with a switched inductor/capacitor: (a) buck derived,...Figure 1.11 (a) Voltage‐fed, (b) current‐fed, and (c) quasi‐Z‐source convert...Figure 1.12 Quasi‐resonant converters: (a) buck type, (b) boost type, and (c...Figure 1.13 Converters with multiple pairs of active–passive switches: (a) h...Figure 1.14 Isolated PWM converters: (a) flyback, (b) forward, (c) push‐pull...Figure 1.15 PWM converters with coupled inductors: (a) buck type, (b) boost ...Figure 1.16 (a) P cell and (b) N cell.Figure 1.17 (a) Tee canonical cell and (b) Pi canonical cell.Figure 1.18 (a) Buck and inverse buck and (b) boost and inverse boost.Figure 1.19 With the same input‐to‐output transfer ratio of (2D − 1)/(1 − D)...Figure 1.20 (a) Switched‐capacitor and (b) switched‐inductor cells.Figure